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<title>VPBROADCASTM—Broadcast Mask to Vector Register </title></head>
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<h1>VPBROADCASTM—Broadcast Mask to Vector Register</h1>
<table>
<tr>
<th>Opcode/Instruction</th>
<th>Op/En</th>
<th>64/32 bit Mode Support</th>
<th>CPUID Feature Flag</th>
<th>Description</th></tr>
<tr>
<td>EVEX.128.F3.0F38.W1 2A /r VPBROADCASTMB2Q xmm1, k1</td>
<td>RM</td>
<td>V/V</td>
<td>AVX512VL AVX512CD</td>
<td>Broadcast low byte value in k1 to two locations in xmm1.</td></tr>
<tr>
<td>EVEX.256.F3.0F38.W1 2A /r VPBROADCASTMB2Q ymm1, k1</td>
<td>RM</td>
<td>V/V</td>
<td>AVX512VL AVX512CD</td>
<td>Broadcast low byte value in k1 to four locations in ymm1.</td></tr>
<tr>
<td>EVEX.512.F3.0F38.W1 2A /r VPBROADCASTMB2Q zmm1, k1</td>
<td>RM</td>
<td>V/V</td>
<td>AVX512CD</td>
<td>Broadcast low byte value in k1 to eight locations in zmm1.</td></tr>
<tr>
<td>EVEX.128.F3.0F38.W0 3A /r VPBROADCASTMW2D xmm1, k1</td>
<td>RM</td>
<td>V/V</td>
<td>AVX512VL AVX512CD</td>
<td>Broadcast low word value in k1 to four locations in xmm1.</td></tr>
<tr>
<td>EVEX.256.F3.0F38.W0 3A /r VPBROADCASTMW2D ymm1, k1</td>
<td>RM</td>
<td>V/V</td>
<td>AVX512VL AVX512CD</td>
<td>Broadcast low word value in k1 to eight locations in ymm1.</td></tr>
<tr>
<td>EVEX.512.F3.0F38.W0 3A /r VPBROADCASTMW2D zmm1, k1</td>
<td>RM</td>
<td>V/V</td>
<td>AVX512CD</td>
<td>Broadcast low word value in k1 to sixteen locations in zmm1.</td></tr></table>
<h3>Instruction Operand Encoding</h3>
<table>
<tr>
<td>Op/En</td>
<td>Operand 1</td>
<td>Operand 2</td>
<td>Operand 3</td>
<td>Operand 4</td></tr>
<tr>
<td>RM</td>
<td>ModRM:reg (w)</td>
<td>ModRM:r/m (r)</td>
<td>NA</td>
<td>NA</td></tr></table>
<p><strong>Description</strong></p>
<p>Broadcasts the zero-extended 64/32 bit value of the low byte/word of the source operand (the second operand) to each 64/32 bit element of the destination operand (the first operand). The source operand is an opmask register. The destination operand is a ZMM register (EVEX.512), YMM register (EVEX.256), or XMM register (EVEX.128).</p>
<p>EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.</p>
<p><strong>Operation</strong></p>
<p><strong>VPBROADCASTMB2Q</strong></p>
<p>(KL, VL) = (2, 128), (4, 256), (8, 512)</p>
<p>FOR j (cid:197) 0 TO KL-1</p>
<p>i (cid:197) j*64</p>
<p>DEST[i+63:i] (cid:197) ZeroExtend(SRC[7:0])</p>
<p>ENDFOR</p>
<p>DEST[MAX_VL-1:VL] (cid:197) 0</p>
<p><strong>VPBROADCASTMW2D</strong></p>
<p>(KL, VL) = (4, 128), (8, 256),(16, 512)</p>
<p>FOR j (cid:197) 0 TO KL-1</p>
<p>i (cid:197) j*32</p>
<p>DEST[i+31:i] (cid:197) ZeroExtend(SRC[15:0])</p>
<p>ENDFOR</p>
<p>DEST[MAX_VL-1:VL] (cid:197) 0</p>
<p><strong>Intel C/C++ Compiler Intrinsic Equivalent</strong></p>
<p>VPBROADCASTMB2Q __m512i _mm512_broadcastmb_epi64( __mmask8);</p>
<p>VPBROADCASTMW2D __m512i _mm512_broadcastmw_epi32( __mmask16);</p>
<p>VPBROADCASTMB2Q __m256i _mm256_broadcastmb_epi64( __mmask8);</p>
<p>VPBROADCASTMW2D __m256i _mm256_broadcastmw_epi32( __mmask8);</p>
<p>VPBROADCASTMB2Q __m128i _mm_broadcastmb_epi64( __mmask8);</p>
<p>VPBROADCASTMW2D __m128i _mm_broadcastmw_epi32( __mmask8);</p>
<p><strong>SIMD Floating-Point Exceptions</strong></p>
<p>None</p>
<p><strong>Other Exceptions</strong></p>
<p>EVEX-encoded instruction, see Exceptions Type E6NF.</p></body></html>